 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| agilent HFCT-701XB, 10 gb ethernet, 1310 nm, 10 km 10gbase-lr, xenpak lan-phy data sheet features ieee std 802.3ae type 10gbase- lr pmd (10 gigabit ethernet standard) compliant with xenpak msa draft 3.0 standard sc duplex fiber optic connector standard 70 pin electrical connector four wide xaui electrical interface mdio management interface only 3.3 v and 1.8 v supplies required (compatible with the xenpak aps) 5 diagnostic loopback modes front panel hot pluggable excellent thermal and emi integrity performance supports high port densities hot plug power up circuit removes psu sequence dependency and reduces inrush current precision onboard oscillator - no external clocks required applications enterprise to metro uplinks campus trunking data aggregation exchange point-to-point links description the HFCT-701XB is an intelligent optical module which incorporates the complete physical layer functionality from the 10.3125 gb/s 64b/66b encoded optical interface to a xaui compliant (4 channel x 3.125 gb/s) 8b/10b encoded electrical interface and vice versa. the control interface (mdio) is also integrated. the HFCT-701XB module includes a transmitter that incorporates an uncooled, directly modulated 1310 nm dfb laser. the receiver subassembly includes a highly reliable pin photodiode. the mux/demux, xaui interface and mdio management functions are all integrated into the module, as is a precision oscillator that removes any need for an external reference clock.
2 table of contents general specifications general optical specifications 3 general electrical specifications 3 environmental specifications 3 technical specifications absolute maximum ratings 4 typical operating conditions 4 optical specifications 5 electrical control and sense i/o parameters 5 electrical specification s 8 mechanical specifications 13 functional descriptions block diagram 17 transmitter path summary 17 receiver path summary 18 management data input output (mdio) interface 18 eeprom interface 19 monitor and diagnostic features 21 loopbacks 24 reset operation 24 internal clock functionality 26 HFCT-701XB registers HFCT-701XB device 1 pma/pmd registers 28 HFCT-701XB device 3 pcs registers 42 HFCT-701XB device 4 phyxs registers 48 regulatory compliance electrostatic discharge (esd) 53 electromagnetic interference (emi) 53 immunity 53 glossary 53 3 general specifications figure 1. high level block diagram general optical specifications optical connector: sc duplex optical line rate: 10.3125 gb/s link length: 10 km, with g.652 fiber laser: 1310 nm, directly modulated, uncooled dfb detector: pin diode electrical connector system control agilent HFCT-701XB 8b/10b 3.125 x 4 serdes mac with rs other signals 8b/10b 3.125 x 4 serdes 64b/66b 10g serdes mdio opto opto optical connectors general electrical specifications connector: 70-pin, mates to tyco/amp part no. 1367337-1 or equivalent supply voltages: +1.8 v and +3.3 v e->o coding (transmit direction): 8b/10b coding removed, 64b/ 66b added o->e coding (receive direction): 64b/66b removed, 8b/10b coding added xaui interface: 100 w differential, ac- coupled i/o on tx and rx, per ieee 802.3ae clause 47 control interface: mdio, 1.2 v, per ieee 802.3ae clause 45.3 non volatile memory: 48 byte user space environmental specifications operating temperature: 0 c to +70 c case power consumption: 6.0 w maximum 4 technical specifications absolute maximum ratings 1 recommended operating conditions 2 notes: 1. absolute maximum ratings are those values beyond which functional performance is not intended, device reliability is not impl ied, and damage to the device may occur. 2. typical operating conditions are those values for which functional performance and device reliability is implied. parameter minimum typical maximum units notes storage temperature 0 85 c operating temperature 0 70 c case temperature supply voltage (3.3 v) 3.6 v supply voltage (1.8 v) 2.0 v voltage on any xaui pin 2.5 v voltage on any lvcmos pin -0.7 4.0 v parameter minimum typical maximum units conditions stabilization time 0.5 5 sec input voltage 3.135 3.3 3.465 v input voltage (aps) 1.71 1.8 1.89 v supply current (@ 3.3 v) 1.5 1.6 a supply current (@ 1.8 v) 0.15 0.4 a power consumption 5.2 6.0 w inrush current during hot plug 50 ma/ms inrush current (per power pin) 0.75 a 150% x 0.5a steady state rating 5 optical specifications parameter minimum typical maximum units notes transmitter laser oma output power -5.2 dbm oma 1, 2 laser mean output power -8.2 0.5 dbm mean 1, 2, 3 extinction ratio 3.5 - db 1, 2 wavelength 1260 1355 nm transmitter and dispersion penalty (tdp) 3.2 db 1, 2 side mode suppression ratio 30 db 1 oma - tdp -6.2 dbm oma 1, 2 rin 12 oma -128 db/hz 1 optical return loss 12 db tx eye definition see figure 2 receiver stressed sensitivity - -10.3 dbm oma 1 nominal sensitivity - -12.6 dbm oma 1, 3 receive power overload 0.5 dbm mean 1, 4 reflectance loss -12 db 1 wavelength 1260 1355 nm 1 signal detect on -30 dbm signal detect off -16 dbm signal detect hysteresis 0.5 db general specification considerations (notes) 1. ieee 802.3ae compliant. 2. these parameters are interrelated: see ieee 802.3ae. 3. information purposes only. 4. up to 1.5 db without damage. note: where x1, x2, x3, y1, y2, y3 = 0.25, 0.40, 0.45, 0.25, 0.28, 0.40 respectively figure 2. transmitter eye mask definition 6 electrical mdio parameters table 2 - mdio 1.2 v dc parameters table 3 - mdio ac parameters parameter description minimum typical maximum units conditions voh output high voltage 1.0 1.5 v ioh = -100 ua vol output low voltage -0.3 0.2 v iol = +100 ua iol output low current -4 ma vin = 0.3 vih input high voltage 0.84 1.5 v vil input low voltage -0.3 0.36 v cin input capacitance 10 pf parameter description minimum typical maximum units conditions thold mdio data hold time 10 ns tsetup mdio data setup time 10 ns tdelay delay from mdc rising edge to mdio data change 0300ns fmax maximum mdc clock rate 2.5 mhz electrical control and sense i/o parameters table 1 - cmos dc parameters (mdc, prtad<4:0>, lasi) parameter description minimum typical maximum units conditions vol output low voltage 0.15 v ext. rpullup = 10 k to 1.2 v voh output high voltage 1.0 1.5 v ext. rpullup = 10 k to 1.2v vih input high voltage 0.84 1.25 v vil input low voltage 0.36 v ipd input pad pulldown current 20 40 120 a vin = 1.2 v trise rise time 30 us cload = 300 pf tfall fall time 25 50 ns cload = 300 pf 7 electrical high speed i/o parameters table 4 - 3.125 gb/s xaui input interface table 5 - 3.125 gb/s xaui driver characteristics parameter description minimum typical maximum units conditions baud rate 3.125 gb/s baud rate tolerance -100 100 ppm differential input amplitude 200 2500 mvpp note 1 differential return loss -10 db 100 mhz to 2.5 ghz ref to 100 impedance common mode return loss -6 db 100 mhz to 2.5 ghz ref to 25 input differential skew 75 ps p-p at crossing point, note 2 jitter amplitude tolerance deterministic + random jitter + sj jitter 0.55 + sj uipp see figure 2a for sj jitter graph parameter description minimum typical maximum units conditions baud rate 3.125 gb/s baud rate variation -100 100 ppm differential amplitude 800 1600 mvpp transition times (20-80%) 60 90 130 ps note 2 total output jitter 0.175 ui no pre-equalization output deterministic jitter 0.085 ui no pre-equalization output differential skew 15 ps at crossing point differential output return loss db 312.5 mhz to 625 mhz: -10 db 625 mhz to 3.125 ghz: as per equation 47-1 ieee 802.3ae electrical eye mask see figure 3 figure 2a. single-tone sinusoidal jitter mask note: 1. maximum amplitude of 2500 mvpp is the combined effect of the driver maximum output signal of 1600 mvpp and the receiver input impedance mismatch. 2. for information only. 8 electrical eye mask figure 3 - xaui driver near end template 800 400 0 -400 -800 differential amplitude (mv) 0 x1 = 0.175 1-x1 = 0.825 1 x2 = 0.390 1-x2 = 0.610 time in ui general connector considerations 1. ground connections are common for tx and rx. 2. v cc contacts are each rated at 0.5 a nominal. 3. see figure 8 for layout of host pcb and location of pin1. 9 table 6 - general i/o pin summary signal type pins direction function power supply pin s ground 1:3, 33:37, 40, 43, 46, 49, 52:54, 57, 60, 63, 66, 69:70 electrical ground 3.3 v 5:6, 30:31 i 3.3 v power supply 5.0 v 4, 32 i 5.0 v power supply not used adaptive power supply 7:8, 28:29 i adaptive power supply (1.8 v) adaptive power supply set 25 i aps set ccnnection adaptive power supply sense 27 i aps sense connection control & sense i/o pins lasi 9 o 1.2 v cmos pull up on host reset 10 i 1.2 v cmos pull up on module transmitter on/off 12 i 1.2 v cmos pull up on module port address 4:0 19:23 i 1.2 v cmos pull up on module mdio pins mod detect 14 o 1 kw pull down to ground on module management data io 17 i/o 1.2 v per ieee802.3ae clause 45.3 management data clock 18 i 1.2 v per ieee802.3ae clause 45.3 high speed i/o pins receiver lane 0:3 + 41, 44, 47, 50 o xaui per ieee802.3ae clause 47 receiver lane 0:3 - 42, 45, 48, 51 o xaui per ieee802.3ae clause 47 transmitter lane 0:3 + 55, 58, 61, 64 i xaui per ieee802.3ae clause 47 transmitter lane 0:3 - 56, 59, 62, 65 i xaui per ieee802.3ae clause 47 non connected pins not connected 4, 11, 13, 15:16, 24, 26, 32, 38:39, 67:68 nc on module 10 electrical pin out 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 prtad2 prtad1 prtad0 not connected aps set not connected aps sense aps aps 3.3v 3.3v 5.0v gnd gnd gnd gnd 5.0v 3.3v 3.3v aps aps lasi reset not connected tx on/off not connected mod detect not connected not connected mdio mdc prtad4 prtad3 gnd gnd 1 2 3 4 5 6 7 8 9 gnd gnd gnd gnd gnd 70 69 53 52 51 49 48 47 46 45 44 43 42 40 39 38 37 36 50 41 not connected not connected gnd tx lane3- tx lane3+ gnd tx lane2- tx lane2+ gnd tx lane1- tx lane1+ gnd tx lane0- tx lane0+ 68 67 66 65 64 63 62 61 59 58 57 56 55 60 gnd 54 gnd rx lane2- rx lane2+ gnd rx lane1- rx lane1+ gnd rx lane0- rx lane0+ gnd not connected not connected rx lane3- rx lane3+ gnd figure 4. electrical pin out 11 electrical pin out definitions table 7 - pin function definitions (lower row) pin no name direction function note 1 gnd electrical ground 2 gnd electrical ground 3 gnd electrical ground 4 not connected 5.0 v power supply 5 3.3 v i 3.3 v power supply 6 3.3 v i 3.3 v power supply 7 aps i adaptive power supply (1.8 v) 8 aps i adaptive power supply (1.8 v) 9 lasi o logic high: normal operation logic low: lasi asserted see table 10 10 reset i logic high: normal operatio logic low: reset 11 not connected 12 tx on/off i pulled up inside module via 10 k logic high: transmitter on logic low: transmitter off 13 not connected 14 mod detect o pulled low inside module through 1 k to gnd 15 not connected 16 not connected 17 mdio i/o management data io 18 mdc i management data clock 19 prtad4 i port address bit 4 20 prtad3 i port address bit 3 21 prtad2 i port address bit 2 22 prtad1 i port address bit 1 23 prtad0 i port address bit 0 24 not connected 25 aps set i aps set connection 26 not connected 27 aps sense i aps sense connection 28 aps i adaptive power supply (1.8 v) 29 aps i adaptive power supply (1.8 v) 30 3.3 v i power 31 3.3 v i power 32 not connected 5.0 v power supply 33 gnd electrical ground 34 gnd electrical ground 35 gnd electrical ground 12 table 8 - pin function definitions (upper row) pin no name direction function note 36 gnd electrical ground 37 gnd electrical ground 38 not connected 39 not connected 40 gnd electrical ground 41 rx lane 0+ o module xaui output lane 0+ 42 rx lane 0- o module xaui output lane 0- 43 gnd electrical ground 44 rx lane 1+ o module xaui output lane 1+ 45 rx lane 1- o module xaui output lane 1- 46 gnd electrical ground 47 rx lane 2+ o module xaui output lane 2+ 48 rx lane 2- o module xaui output lane 2- 49 gnd electrical ground 50 rx lane 3+ o module xaui output lane 3+ 51 rx lane 3- o module xaui output lane 3- 52 gnd electrical ground 53 gnd electrical ground 54 gnd electrical ground 55 tx lane 0+ i module xaui input lane 0+ 56 tx lane 0- i module xaui input lane 0- 57 gnd electrical ground 58 tx lane 1+ i module xaui input lane 1+ 59 tx lane 1- i module xaui input lane 1- 60 gnd electrical ground 61 tx lane 2+ i module xaui input lane 2+ 62 tx lane 2- i module xaui input lane 2- 63 gnd electrical ground 64 tx lane3+ i module xaui input lane 3+ 65 tx lane3- i module xaui input lane 3- 66 gnd electrical ground 67 not connected 68 not connected 69 gnd electrical ground 70 gnd electrical ground 13 mechanical specifications package dimensions figure 5. note: it is recommended that the user refers to the xenpak msa at www.xenpak.org for full mechanical detail. 14 key values tolerance comments mm inch mm a1 51.3 2.020 0.20 width of bezel overall b1 22.4 0.882 0.20 height of bezel overall e1 20.75 0.817 maximum extension of captive screw f1 36.0 1.417 0.20 width of transceiver body k1 (121.0) 4.764 ref length of transceiver overall minus protruding captive screw heads l1 5.00 0.197 0.20 length of captive screw from datum "d" to end of threaded end n1 5.8 0.228 0.20 datum "d" to front of transceiver bezel v1 7.92 0.312 0.20 datum "e" to bottom of transceiver bezel y1 102.20 4.024 0.20 datum "d" to datum "b" aa1 3.0 0.118 0.50 datum "b" to end of 45 chamfer bb1 (115.2) 4.535 ref length of module from datum "d" to rear over-hanging ledge ll1 25.8 1.016 maximum length of thumbscrew dimensions table (figure 5) 15 figure 6. 16 note: case ground is separated from the common rx and tx signal ground figure 7. 17 pin1 figure 8. host board layout for 70 pin connector 18 functional descriptions block diagram figure 9 shows a block diagram of the HFCT-701XB. figures 10 and 11 show greater detail of the transmitter and receiver paths. electrical connector system control HFCT-701XB other signals 8b/10b 3.125 x 4 serdes 64b/66b 10g serdes mdio opto opto optical connectors figure 9. block diagram of HFCT-701XB figure 10. transmit path high level overview transmitter path summary figure 10 shows a block diagram of the transmit path, from the four xaui differential inputs to the optical output. the incoming 4 x 3.125 gb/s xaui differential 8b/10b encoded electrical inputs, are reformatted and transmitted onto the outgoing fiber optic interface at 10.3125 gb/s, using 64b/66b encoding. sipo and code word alignment, with |k| char lane alignment, with |a| character. pll scrambler 1+x 39 +x 58 rate adjust & frame xaui lane 1 xaui lane 2 xaui lane 3 xaui lane 0 64b/66b 1:0 block sync tx opto pll tx xtal mux 8b/10b decoder 64b/66b encoder rate adjust by add drop off |r| character cdr 19 receiver path summary figure 11 shows a block diagram of the receiver path, from the incoming 10.3125 gb/s, 64b/66b encoded optical interface to the four 3.125 gb/s differential 8b/ 10b encoded xaui electrical output interface. the xaui output drivers provide low- swing differential output with 100 w differential output impedance and are ac coupled. management data input/output (mdio) interface the mdio interface provides a simple, two wire, serial interface to connect a station management entity (sta) and a managed phy for the purpose of controlling the phy and gathering status from the phy. the management interface consists of the two wire physical interface, a frame format, a protocol specification for exchanging the frames and a register set that can be read and written using these frames. the two wires of the physical interface are the management data clock (mdc) and the management data i/o (mdio). figure 11. receive path high level overview management data clock (mdc) the mdc is sourced by the station management entity (sta) to the phy as the timing reference for transfer of information on the mdio signal. mdc is an aperiodic signal that has no maximum high or low times. management data i/o (mdio) mdio is a bidirectional signal between the phy (HFCT-701XB) and the sta. it is used to transfer control and status information. data is always driven and sampled synchronously with respect to mdc. figure 13 shows that mdio open drain driver configuration. mdio timing relationship to mdc mdio is a bidirectional signal that can be sourced by the sta or the HFCT-701XB. when the sta sources the mdio signal, the sta shall provide a minimum of 10 ns of setup time and a minimum of 10 ns of hold time referenced to the rising edge of mdc (see figure 12). when the mdio signal is sourced by the HFCT-701XB, it is sampled by the sta synchronously with respect to the rising edge of mdc. the clock output delay from the HFCT-701XB shall be a minimum of 0 ns and a maximum of 300 ns. mdc mdio (sta sourced) tsu=10 ns min data valid thd=10 ns min mdc mdio (HFCT-701XB sourced) data valid tpd=0 ns min, 300 ns max figure 12. mdio/mdc timing pll descrambler 1+x 39 +x 58 frame recovery (block sync) xaui lane 1 xaui lane 2 xaui lane 3 xaui lane 0 driver rx opto de mux xtal 8b/10b encoder 64b/66b decoder rate adjust mux cdr clock for rx 10g path 20 open drain driver coregnd mdio pin 1.2 v pullup, r>100 ohms external capacitance loading c< 700 pf receive buffer figure 13. mdio open drain driver configuration table 9. frame format management frame format the HFCT-701XB has an internal address register which is used to store the address for mdio reads and writes. this mdio address register can be set by using an address frame that specifies the register address to be accessed within a particular port device. the following write, read or a post-read-increment-address frame to the same port device shall access the register whose address is stored in the hfct- 701xb mdio address register. an address frame should be followed immediately by its associated write, read or post- read-increment-address frame. upon receiving a post-read- increment-address frame and having completed the read operation, the HFCT-701XB shall increment and store the address of the register accessed. if no address cycle is received before the next write, read or post-read-increment-address frame, then the HFCT-701XB shall use the stored address for that register access. the management frame format for indirect access is specified in table 9. pre - preamble at the beginning of each transaction the sta shall send a preamble sequence of 32 contiguous logic one bits on mdio with 32 corresponding cycles on mdc, to provide the HFCT-701XB with a pattern that it can use to establish synchronization. the hfct- 701xb must observe this preamble sequence before it responds to any transaction. st - start the start of frame is indicated by a <00> pattern. this pattern ensures transitions from the default logic one line to zero and back to one. management frame fields frame pre st op prtad devad ta addr/data idle address 1...1 00 00 prtad[4:0] da[4:0] 10 d[15:0] z write 1...1 00 01 prtad[4:0] da[4:0] 10 d[15:0] z read 1...1 00 11 prtad[4:0] da[4:0] z0 d[15:0] z read inc 1...1 00 10 prtad[4:0] da[4:0] z0 d[15:0] z op - operation code table 10. op code definitions prtad the port address is five bits, allowing 32 unique port addresses. HFCT-701XBs port address is set through pins prtad<0:4>. devad the device address is five bits, allowing 32 unique devices per port. the HFCT-701XB supports device addresses 1 (pma/pmd), 3 (pcs) and 4 (phy xs). ta the turnaround time is a two bit time spacing between the register address field and the data field of a management frame to avoid contention during a read transaction (see ieee 802.3ae). op code operation 00 register address 01 write data 11 read data 10 post read data + increment addr/data the data/address field is 16 bits. the first bit transmitted/ received is bit 15 and the last bit is bit 0. idle the idle condition is a high- impedance state. the mdio line will be pulled to a one. eeprom interface nvr there are two main memory/ register types in the hfct- 701xb which comply with the ieee 802.3ae and xenpak standard: volatile and nonvolatile. these areas can be further divided into user readable and writeable areas. at power up the module register space is initialized and, where appropriate, default values are loaded from the non user accessible nonvolatile memory. the user accessible nonvolatile memory is also uploaded entirely into the user accessible volatile memory. 21 figure 14. mdio frame formats mdc mdio write 32 "1"s 0000 a4 a3 a0 r4 r3 r0 0 1 a15 a14 a1 a0 idle preamble st op code phy address register address turn around address idle write device management interface - address frame structure mdc mdio write 32 "1"s 0001 a4 a3 a0 r4 r3 r0 0 1 d15 d14 d1 d0 idle preamble st op code phy address register address turn around data idle write device management interface - write frame structure mdc mdio read increment 32 "1"s 0010 a4 a3 a0 r4 r3 r0 0 z d15 d14 d1 d0 idle preamble st op code phy address register address turn around data idle write device management interface - read increment frame structure read mdc mdio read 32 "1"s 0011 a4 a3 a0 r4 r3 r0 0 z d15 d14 d1 d0 idle preamble st op code phy address register address turn around data idle write device management interface - read frame structure read 22 it is important to note that writes to the user accessible volatile memory are not stored to the corresponding user nonvolatile area and will therefore be lost upon a power down or reset. for such writes to be permanent the data must be written first to the user accessible nonvolatile area and then a reload invoked via the nvr control/status register, see register 1.32768. access the xenpak msa related nonvolatile control/status register is only needed for performing writes to the nonvolatile user accessible area within the HFCT-701XB because nonvolatile memory cannot be written to by normal mdio write cycles. other writes to volatile memory and registers may be performed directly via normal mdio write cycles. all volatile and nonvolatile locations may be read directly via mdio read cycles, it is not necessary to use the nvr control/status register, other than for status. read/write command (bit5) the xenpak msa related 1.32768.5 register must be set to 1 to perform writes to the nvr and zero (read) otherwise a zero written to bit 5 initiates an nvr read. a 1 written to bit 5 initiates an nvr write. if the nvr register bit 5 is set to zero and the extended command bits set to 11 forces an upload of all values in the nvr to the volatile areas, including default register values. such an upload is performed automatically after a hard or soft reset. eeprom checksum checking the HFCT-701XB will perform a checksum calculation and compare after every successful 256 byte read. the checksum for comparison is in eeprom register 118 =mdio register 1.32893.7:0. the checksum is equal to the 8 lsb s of the sum of bytes 0 to 117 of the eeprom. the calculated checksum is stored in mdio register 1.49156.15:8. the result of the calculated checksum compared with the one read from eeprom is placed in mdio register 1.49155.7. eeprom 256 byte read cycle an eeprom 256 byte read cycle is initiated by setting mdio bits 1.32768.0,1 to 0 and 1.32768.5 to 0. the information to be read from the eeprom stored in the 256 mdio registers. a 256 byte read is initiated on hot plug or reset. eeprom single byte read or write cycle an eeprom single byte read/ write cycle is initiated by setting mdio eeprom control register bits 1.32768.1:0 to 10. as for the 256 byte read/write commands, mdio register 1.32768.5 determines if a read or a write cycle will be performed. the single byte eeprom address is read from eeprom control register 1.32768 bit15:8. the data is placed in/read from the associated mdio register. monitors and diagnostic features the lasi pin is used to indicate suboptimal performance in either the receive or transmit path. it can be used as an interrupt. it is the or of the tx_alarm, rx_alarm and the ls_alarm signals each gated with their respective enables. the enables are read from mdio register 1.36867, lasi control. lasi ={or of (reg 1.36869.n bit wise and reg 1.36866.n) for n=0 to 15}. description mdio status registers type mdio enable registers default value ls_alarm 1.36869.0 ro/lh 1.36866.0 0 tx_alarm 1.36869.1 ro/lh 1.36866.1 0 rx_alarm 1.36869.2 ro/lh 1.36866.2 0 lasi test mode 1.36869.3 rw 1.36866.3 0 1.8 v supply too low 1.36869.4 ro/lh 1.36866.4 0 3.3 v supply too low 1.36869.5 ro/lh 1.36866.5 0 mon3p3v_in voltage too low 1.36869.6 ro/lh 1.36866.6 0 table 11. lasi control registers 23 ls_alarm ls alarm is latched high each time the link_status signal changes state. ls_alarm is the output of this latch and the ls_alarm enable register (see figure 15). link_status is an indicator of the link health. link_status = {pmd signal detect (mdio 1.10.0) and pcs block_lock (mdio 3.32.0) and phy_xs lane_alignment (mdio 4.24.12)} description mdio status registers (ro) mirrors type mdio enable registers (r/w) default phy_xs receive local fault 1.36867.0 4.8.10 ro/lh 1.36864.0 1 phy_xs receive rate error 1.36867.1 1.49154.3 ro/lh 1.36864.1 0 pcs receive code violation 1.36867.2 ro/lh 1.36864.2 0 pcs receive local fault 1.36867.3 3.8.11 ro/lh 1.36864.3 0 pma receive local fault 1.36867.4 1.8.11 ro/lh 1.36864.4 1 receive power error 1.36867.5 ro/lh 1.36864.5 0 table 12. receive alarm registers figure 15. tx lasi signals 1 * phy xgxs tx local fault 4.8.11 = 1 (en 1.36865.0=1) 2 * phy xgxs tx code error 1.36868.1 = 1 (en 1.36865.1=1) 3 * phy xgxs tx rate error 1.49154.5 = 1 (en 1.36865.2=1) 4 * pcs local tx fault 3.8.11 = 1 (en 1.36865.3=1) 5 * pma local tx fault 1.8.11 = 1 (en 1.36865.4=1) 6 * tx pll latched loss of lock 1.36868.5 = 1 (en 1.36865.5=1) 7 * latched version of tx fault 1.36868.6 = 1 (en 1.36865.6=1) sipo and code word a lignment, with |k| ch ar lane alignment, with |a| character. pll s crambler 1+ x 39 +x 58 rate adjust & frame xaui lane 1 xaui lane 2 xaui lane 3 s tatus 4 xaui lane 0 status 1,2 status 1,3 64b/66b 1:0 block sync tx opto pll tx xtal tx pll ok 1.49153.0 status 4 status 5 status 6 mux 8 b/10b decod er 6 4b/66b encod er r ate adjust by add dro p o ff |r| charact er cdr rx_alarm rx_alarm is used to indicate a problem with the receive path. rx_alarm is the or of several receive path status registers in mdio register 1.36867. the oring of each term is enabled by a companion mdio register in 1.36864 and the overall output is enabled by the rx_alarm enable register (1.36866.2). rx_alarm ={or of (reg 1.36867 bit wise and reg 1.36864..n) for n=0 to 15} and {rx_alarm enable (1.36866.2}) 24 table 13. transmit alarm registers figure 16. lasi functional diagram tx_alarm tx_alarm is used to indicate a problem with the transmit path. tx_alarm is the or of several transmit path status registers in mdio registers 1.36868 bit wise description mdio status registers (ro) mirrors type mdio enable registers (r/w) default phy_xs transmit local fault 1.36868.0 4.8.11 ro/lh 1.36865.0 1 phy_xs code error 1.36868.1 - ro/lh 1.36865.1 0 phy_xs transmit rate error 1.36868.2 1.49154.5 ro/lh 1.36865.2 0 pcs transmit local fault 1.36868.3 3.8.11 ro/lh 1.36865.3 1 pma transmit local fault 1.36868.4 1.8.11 ro/lh 1.36865.4 1 latched version of txlock 1.36868.5 1.49153.0 ro/lh 1.36865.5 0 latched version of txfault 1.36868.6 ro/lh 1.36865.6 1 tx output power fault 1.36868.7 ro/lh 1.36865.7 0 laser temperature fault 1.36868.8 ro/lh 1.36865.8 0 laser bias current fault 1.36868.9 ro/lh 1.36865.9 0 andd with the tx_alarm enable register. the oring of each term is enabled by a companion mdio register in 1.36865. tx_alarm = {or of (reg 1.36868 bit wise and reg 1.36865) for n=0 to 15} and {tx_alarm enable (reg 1.36866.1)} 1 * phy xgxs tx local fault 4.8.11 = 1 and (en 1.36865.0=1) 2 * phy xgxs tx code error 1.36868.1 = 1 and (en 1.36865.1=1) 3 * phy xgxs tx rate error 1.49154.5 = 1 and (en 1.36865.2=1) 4 * pcs local tx fault 3.8.11 = 1 and (en 1.36865.3=1) 5 * pma local tx fault 1.8.11 = 1 and (en 1.36865.4=1) 6 * tx pll latched loss of lock 1.36868.5 = 1 and (en 1.36865.5=1) 7 * latched version fo tx fault 1.36868.6 = 1 and (en 1.36865.6=1) 1 * phy xgxs rx local fault 4.8.10 = 1 and (en 1.36864.0=1) 2 * phy xgxs rx rate error 4.49154 = 1 and (en 1.36864.1=1) 3 * 64b/66b rx code violation 1.36867 = 1 and (en 1.36864.2=1) 4 * pcs local rx fault 3.8.11 = 1 and (en 1.36864.3=1) 5 * pma/d rx fault 1.8.10 and (en 1.36864.4=1) 6 * rx power error 1.49155.5 and (en 1.36864.5=1) 1 * pmd signal detect 1.10.0 (en 1.36864.0=1) 1 * pcs block_lock 3.32.0 (en 1.36864.0=1) 1 * phy_xs lane alignment 4.24.12 (en 1.36864.0=1) ls_alarm 1.36869.0 (en 1.36866.0 0) tx_alarm 1.36869.1 (en 1.36866.1 0) rx_alarm 1.36869.2 (en 1.36866.2 0) lasi test mode 1.36869.3 (en 1.36866.3 0) 1.8v supply too low 1.36869.4 (en 1.36866.4 0) 3.3v supply too low 1.36867.5 (en 1.36866.5 0) latch lin k_status latch high on change of level reset low ls_alarm ls_alarm_enable tx_alarm tx_alarm_enable rx_alarm rx_alarm_enable lasi asserted on leading edge of read 25 loopbacks when in any system (pma, pcs or xgxs system) loopback mode the HFCT-701XB shall accept data from the transmit path and return it on the receive path. during pma loopback the xenpak module will transmit the data received at the xaui i/ ps. in xgxs system loopback, the laser will default to mean power but without any modulation. in pcs loopback mode a continuous pattern of 0x0f0f will be output. transmit data will be output instead if the associated loopback data out enable bit is set high for the enabled loopback mode. when in pma network loopback mode, the recovered and retimed 10.3125 gbd signal is looped to the transmitter. the receive path xaui output data will be received data. xaui idle codes will be output instead of the received data if the network loopback data out enable bit is set high. in ieee 802.3ae standard xgxs network loopback the recovered received data is looped back to the transmit path in the xaui block. enabling of more than one loopback path is invalid. loopback name loopback direction loopback control register bypassed path default output data output enable register bypassed path output control' =1 pma system loopback[ 1] tx -> rx 1.0.0 transmit data na na pcs loopback tx -> rx 3.0.14 0f0f 3.49152.5 transmit data xgxs network loopback (802.3ae standard) rx -> tx 4.0.14 receive data at rx xaui na na xgxs system loopback tx -> rx 4 4.49152.14 mean power, no modulation 4.49152.15 transmit data pma network loopback rx -> tx 1 1.49153.4 received data 1.49153.9 idle at rxxaui table 14. loopback summary reset operation writing a 1 to any of mdio registers 1.0.15, 3.0.15 or 4.0.15 causes all the HFCT-701XB registers to be reset to their default values. these bits are all self-clearing after the reset function is complete. pulling the reset pin low causes a full chip reset. writes to any bits of the control register while the reset is asserted are ignored. all status and control registers are reset to their default states. the nvr read sequence is started when reset goes high. mdio register bits 1.0.15, 3.0.15, and 4.0.15 will be held to 1 until the reset sequence is complete. [1] pma system loopback requires a valid optical signal to be present on the rx to operate. however, if no valid optical signa l exists, set bit 1.49153.10=1, then set 1.0 bit 0=1. 26 figure 17. HFCT-701XB loopback modes phy xs network loopback lane 0 pll descrambler 1+x 39 +x 58 frame recovery (block sync) xaui lane 1 xaui lane 2 xaui lane 3 enable network loopback 4.0.14=1 xaui lane 0 driver enable system loopback 4.49152.15=1 rx opto de mux xtal 8b/10b encoder 64b/66b decoder rate adjust mux cdr enable system loopback 4.49152.14=1 sipo and code word alignment, with |k| char lane alignment, with |a| character. pll scrambler 1+x 39 +x 58 rate adjust & frame xaui lane 1 xaui lane 2 xaui lane 3 xaui lane 0 cdr 64b/66b 1:0 block sync tx opto pll tx xtal force 1's on phy_xs loopback 4.49152.15=0 pma network loopback 1.49153.4=1 system loopback 1.0.0=1 mux 8b/10b decoder 64b/66b encoder phy xgxs system loopback lane 0 pcs system loopback xgxs system loopback 4.49152.14 xgxs network loopback 4.0.14=1 rate adjust by add drop off |r| character pma network loopback pma system loopback 27 internal clock functionality figure 18. transmit path figure 19. receive path sipo and code word alignment, with |k| char lane alignment, with |a| character. pll scrambler 1+x 39 +x 58 rate adjust & frame xaui lane 1 xaui lane 2 xaui lane 3 xaui lane 0 64b/66b 1:0 block sync tx opto pll tx xtal mux 8b/10b decoder 64b/66b encoder rate adjust by add drop off |r| character tx xaui clock domain recovered from incoming xaui link tx 10g clock domain derrived internally from precision oscillator cdr rx xaui clock domain derived internally from precision oscillator rx 10g clock domain recovered from incoming 10g link pll descrambler 1+x 39 +x 58 frame recovery (block sync) xaui lane 1 xaui lane 2 xaui lane 3 xaui lane 0 driver rx opto de mux xtal 8b/10b encoder 64b/66b decoder rate adjust mux cdr clock for rx 10g path 28 HFCT-701XB registers figure 20. summary of key receiver path registers figure 21. summary of key transmit path registers pll descrambler 1+x 39 +x 58 frame recovery (block sync) xaui lane 1 xaui lane 2 xaui lane 3 reset all x.15 = 1 xaui lane 0 driver bypass scrambler 3.49152.1 =1 reset pcs 3.49152.4=1 pma locked 1.1.2=1 rx opto de mux signal detect 1.10.0=1 rx clk rate error 1.49153.1 =1 1 * phy xgxs rx local fault 4.8.10 = 1 (en 1.36864.0=1) 2 * phy xgxs rx rate error 4.49154.6:9 = 1 (en 1.36864.1=1) 3 * 64b/66b rx code violation 1.36867.2 = 1 (en 1.36864.2=1) 4 * pcs local rx fault 3.8.10 = 1 (en 1.36864.3=1) 5 * pma/d rx fault 1.8.10 (en 1.36864.4=1) 6 * rx power error 1.36867.5 (en 1.36864.5=1) pll ok 4.49152.3 xtal reset tx xgxs 4.49152.0=1 in service pcs bit error counter 3.33.13:8 in service errored block counter 3.33.7:0 status 1,2 status 1 status 3,4 from de-scrambler frame recovery cdr status 4 status 5 8b/10b encoder 64b/66b decoder rate adjust mux cdr status 6 clock for rx 10g path lock 4.49152.7:4 sync 4.24.3:0 lanes aligned 4.24.12=1 pll ok 4.49152.3 phy xgxs link up 4.1.2 = 1 bypass 3.49152.2 =1 reset pcs 3.49152.3=0 transmit disable 1.9.0 1 * phy xgxs tx local fault 4.8.11 = 1 (en 1.36865.0=1) 2 * phy xgxs tx code error 1.36868.1 = 1 (en 1.36865.1=1) 3 * phy xgxs tx rate error 1.36868.2 = 1 (en 1.36865.2=1) 4 * pcs local tx fault 3.8.11 = 1 (en 1.36865.3=1) 5 * pma local tx fault 1.8.11 = 1 (en 1.36865.4=1) 6 * tx pll latched loss of lock 1.36868.5 = 1 (en 1.36865.5=1) 7 * latched version fo tx fault 1.36868.6 = 1 (en 1.36865.6=1) sipo and code word alignment, with |k| char lane alignment, with |a| character. pll scrambler 1+x 39 +x 58 rate adjust & frame xaui lane 1 xaui lane 2 xaui lane 3 status 4 xaui lane 0 legend * = lasi signal status 1,2 status 1,3 64b/66b 1:0 block sync from rx 64b/66b encoder error 3.49152.0 = 1 tx opto pll tx xtal tx pll ok 1.49153.0 status 4 status 5 status 6 mux 8b/10b decoder 64b/66b encoder rate adjust by add drop off |r| character reset all x.15 = 1 cdr 29 HFCT-701XB device 1 pma/pmd registers device from decimal hex to decimal hex register name 10 0 pma/pmd control 1 11 1 pma/pmd status 1 1 2 2 3 3 device identifier 1 4 4 pma/pmd speed ability 15566devices in package 1 7 7 10g pma/pmd control 2 1 8 8 10g pma/pmd status 2 1 9 9 10g pmd transmit disable 1 10 a 10g pmd receive signal detect 114e 15f package identifier (oui) 1 32768 8000 nvr control/status 1 32775 8007 xenpak msa version supported 1 32776 8008 32777 8009 nvr size in bytes 1 32778 800a 32779 800b number of bytes used 1 32780 800c basic field address 1 32781 800d customer field address 1 32782 800e vendor field address 1 32783 800f 32784 8010 extended vendor field address 1 32785 8011 reserved 1 32786 8012 transceiver type 1 32787 8013 optical connector type 1 32788 8014 bit encoding 1 32789 8015 32790 8016 nominal bit rate in multiples of 1mb/s 1 32791 8017 protocol type 1 32792 8018 32801 8021 standards compliance codes 10gbe code byte 0 1 32802 8022 32803 8023 specifies transmission range in 10 m increments 1 32804 8024 32805 8025 fibre type byte 0 and byte1 1 32806 8026 32808 8028 centre optical wavelength in 0.01nm steps - channel 0 1 32818 8032 32821 8035 package identifier oui 1 32822 8036 32825 8039 transceiver vendor oui 30 device from decimal hex to decimal hex register name 1 32826 803a 32841 8049 transceiver vendor name in ascii 1 32842 804a 32857 8059 part number provided by transceiver vendor in ascii 1 32858 805a 32859 805b revision level for part number provided by vendor ascii 1 32860 805c 32875 806b vendor serial number in ascii 1 32876 806c 32885 8075 vendor manufacturing date code in ascii 1 32886 8076 5 v stressed environment reference 1 32887 8077 3.3 v stressed environment reference 1 32888 8078 aps stressed environment reference 1 32889 8079 nominal aps voltage 1 32890 807a dom capability 1 32891 807b reserved 1 32893 807d basic field checksum 1 32894 807e 32941 80ad customer writeable area 1 32942 80ae 33030 8106 vendor specific 1 33031 8107 36863 8fff extended vendor specific 1 36864 9000 rx_alarm control 1 36865 9001 tx_alarm control 1 36866 9002 lasi control 1 36867 9003 rx_alarm status 1 36868 9004 tx_alarm status 1 36869 9005 lasi status 1 49153 c001 extended pma features 1 49155 c003 pma/pmd vendor specific 1 49156 c004 pma/pmd vendor specific checksum 1 49188 c024 pma vendor specific 31 register 1.0 - pma/pmd control 1 register 1.1 - pma/pmd status 1 register 1.2 to 1.3 - device identifier register 1.4 pma/pmd speed ability note: 1. rw = read/write, ro = read only, ll = latching low bit(s) name description r/w 1 default value 1.0.15 reset 1 = pma/pmd reset 0 = normal operation rw 1.0.14 reserved value always 0, writes ignored rw 1.0.13 speed selection 1 = operation at 10 gb/s and above 0 = unspecified rw 1 1.0.12 reserved value always 0, writes ignored rw 1.0.11 low power 1 = low power mode 0 = normal operation rw 0 1.0.10:7 reserved value always 0, writes ignored rw 1.0.6 speed selection 1 = operation at 10 gb/s and above 0 = unspecified rw 1 1.0.5:2 speed selection 5 4 3 2 1 x x x = reserved x 1 x x = reserved x x 1 x = reserved 0 0 0 1 = reserved 0 0 0 0 = 10 gb/s rw 1.0.1 reserved values always 0, writes ignored rw 1.0.0 pma loopback 1 = enable pma loopback mode 0 = disable pma loopback mode rw 0 bit(s) name description r/w 1 default value 1.1.15:8 reserved n/a ro 1.1.7 fault 1 = local fault condition detected in pma/pmd 0 = local fault condition not detected in pma/pmd (set to a 1 when either 1.8.11 or 1.8.10 set to a one) ro n/a 1.1.6:3 reserved n/a ro/ll 1.1.2 receive link status 1 = pma locked to receive signal 0 = pma not locked to receive signal ro/ll n/a 1.1.1 power down ability 1 = pma/pmd supports low power mode 0 = pma/pmd does not support low power mode ro 1 1.1.0 reserved n/a bit(s) name description r/w 1 default value 1.3.15:0 pma identifier ro 1.2.15:0 pma identifier ro bit(s) name description r/w 1 default value 1.4.15:1 reserved for future speeds ro n/a 1.4.0 10 g capable 1 = pma/pmd is capable of operating at 10 gb/s 0 = pma/pmd is not capable of operating at 10gb/s ro 1 32 register 1.5 to 1.6 - pma/pmd devices in package register 1.7 - 10 g pma/pmd control 2 note: 1. rw = read/write, ro = read only, bit(s) name description r/w 1 default value 1.6.15 vendor specific device 2 present 1 = vendor specific device 2 present in package 0 = vendor specific device 2 not present in package ro 1 1.6.14 vendor specific reserved ro 1.6.13:0 reserved n/a ro 1.5.15:6 reserved n/a ro 1.5.5 dte xs present 1 = dte xs present in package 0 = dte xs not present in package ro 0 1.5.4 phy xs present 1 = phy xs present in package 0 = phy xs not present in package ro 1 1.5.3 pcs present 1 = pcs present in package 0 = pcs not present in package ro 1 1.5.2 wis present 1 = wis present in package 0 = wis not present in package ro 0 1.5.1 pmd/pma present 1 = pmd/pma present in package 0 = pmd/pma not present in package ro 1 1.5.0 clause 22 registers present 1 = clause 22 registers present in package 0 = clause 22 registers not present in package ro 0 bit(s) name description r/w 1 default value 1.7.15:3 reserved n/a 1.7.2:0 pma/pmd type selection 2 1 0 1 1 1 = 10gbase-sr pma/pmd type 1 1 0 = 10gbase-lr pma/pmd type 1 0 1 = 10gbase-er pma/pmd type 1 0 0 = 10gbase-lx4 pma/pmd type 0 1 1 = 10gbase-sw pma/pmd type 0 1 0 = 10gbase-lw pma/pmd type 0 0 1 = 10gbase-ew pma/pmd type 0 0 0 = reserved rw 110 33 register 1.8 - 10 g pma/pma status 2 register 1.9 - 10 g pmd transmit disable note: 1. rw = read/write, ro = read only, lh = latch high, clear on read (note that if the condition exitsts following register read, the bit will not be cleared). bit(s) name description r/w 1 default value 1.8.15:14 device present 15 14 1 0 = device responding at this address 1 1 = no device responding at this address 0 1 = no device responding at this address 0 0 = no device responding at this address ro 10 1.8.13 transmit local fault ability 1 = pma/pmd has the ability to detect a local fault condition on the transmit path 0 = pma/pmd does not have the ability to detect a fault condition on the transmit path ro 1 1.8.12 receive local fault ability 1 = pma/pmd has the ability to detect a local fault condition on the receive path 0 = pma/pmd does not have the ability to detect a fault condition on the receive path ro 1 1.8.11 transmit local fault 1 = local fault condition on transmit path 0 = no local fault condition on transmit path ro/lh n/a 1.8.10 receive local fault 1 = local fault condition on receive path 0 = no local fault condition on receive path ro/lh n/a 1.8.9 reserved n/a ro 1.8.8 pmd transmit disable ability 1 = pmd has the ability to disable the transmit path 0 = pmd does not have the ability to disable the transmit path ro 1 1.8.7 10gbase-sr ability 1 = pma/pmd is able to perform 10gbase-sr 0 = pma/pmd is not able to perform 10gbase-sr ro 0 1.8.6 10gbase-lr ability 1 = pma/pmd is able to perform 10gbase-lr 0 = pma/pmd is not able to perform 10gbase-lr ro 1 1.8.5 10gbase-er ability 1 = pma/pmd is able to perform 10gbase-er 0 = pma/pmd is not able to perform 10gbase-er ro 0 1.8.4 10gbase-lx4 ability 1 = pma/pmd is able to perform 10gbase-lx4 0 = pma/pma is not able to perform 10gbase-lx4 ro 0 1.8.3 10gbase-sw ability 1 = pma/pmd is able to perform 10gbase-sw 0 = pma/pmd is not able to perform 10gbase-sw ro 0 1.8.2 10gbase-lw ability 1 = pma/pmd is able to perform 10gbase-sw 0 = pma/pmd is not able to perform 10gbase-lw ro 0 1.8.1 10gbase-ew ability 1 = pma/pmd is able to perform 10gbase-ew 0 = pma/pmd is not able to perform 10gbase-ew ro 0 1.8.0 pma loopback ability 1 = pma has the ability to perform a loopback function 0 = pma does not have the ability to perform a loopback function ro 1 bit(s) name description r/w 1 default value 1.9.15:5 reserved n/a rw 1.9.4:1 lx4 signal detect not used rw 0 1.9.4:0 pmd transmit disable 1 = transmit disable 0 = transmit enable rw 0 34 register 1.10 - 10 g pmd receive signal ok register 1.14 to 1.15 - package identifier (oui) register 1.32768 - nvr control/status 1.32775 to 1.32782 - nvr information bit(s) name description r/w 1 default value 1.10.15:5 reserved value always 0, writes ignored ro 1.10.4:1 lx4 signal detect not used ro 1.10.0 global pmd receive signal detect 1 = signal detected on receive 0 = signal not detected on receive ro bit(s) name description r/w 1 default value 1.15.15 reserved reserved ro 248 1.15.14:11 revision number revision number ro 1.15.11:8 nvr address nvr dev address ro 1.15.7:6 nvr address nvr dev address ro 1.15.5:0 package identifier xenpak oui ro 1.14.15:8 package identifier xenpak oui ro 34 1.14.7:0 package identifier xenpak oui ro bit(s) name description r/w 1 default value 1.32768.15:8 vendor specific rw 1.32768.7:6 reserved n/a ro 1.32768.5 read/write command 3 0 = read nvr 1 = write nvr rw 2 1.32768.4 reserved n/a ro 1.32768.3:2 command status 00 = idle 01 = command completed successfully 10 = command in progress 11 = command failed ro/lh 1.32768.1:0 extended commands 00 = reserved 01 = reserved 10 = read/write 1 byte 11 = read all nvr contents rw 2 bit(s) name description r/w 1 default value (dec) 1.32775.7:0 version nvr version number (msb:lsb) ro 30 1.32776.7:0 nvr_size nvr size (upper byte) = 256 bytes ro 1 1.32777.7:0 nvr_size nvr size (lower byte) = 256 bytes ro 0 1.32778.7:0 mem_used bytes used (upper byte) = 256 bytes ro 1 1.32779.7:0 mem_used bytes used (lower byte) = 256 bytes ro 0 1.32780.7:0 basic addr basic field address (msb:lsb) start ro 11 1.32781.7:0 cust addr customer field address (msb:lsb) start ro 119 1.32782.7:0 vend addr vendor field address (msb:lsb) start ro 167 1.32783.7:0 ext vend addr extended vendor field address start ro 1 1.32784.7:0 ext vend addr extended vendor field address start ro 0 1.32785.7:0 reserved ro 0 note: 1. rw = read/write, ro = read only, lh = latch high, clear on read (note that if the condition exists following register read, t he bit will not be cleared). 2. the values of the ?command? and ?extended command? bits are held until a command has been executed. 3. writes to register 1.32768 ignored during ?command in progress?. reads will not clear command status. 35 register 1.32786 - transceiver type register 1.32787 - optical connector type register 1.32788 - bit encoding register 1.32789 to 1.32790 - bit rate register 1.32791 - protocol type register 1.32792 to 1.32793 - 10gbe compliance code register 1.32802 to 1.32803 - transmission range register 1.32804 to 1.32805 - fiber type suitability register 1.32806 to 1.32808 - center wavelength note: 1. rw = read/write, ro = read only. bit(s) name description r/w 1 default value (dec) 1.32786.7:0 transceiver type xenpak ro 1 bit(s) name description r/w 1 default value (dec) 1.32787.7:0 connector sc duplex connector ro 1 bit(s) name description r/w 1 default value (dec) 1.32788.7:0 bit encoding nrz ro 1 bit(s) name description r/w 1 default value (dec) 1.32789.7:0 bit rate bit 15 (msb) to bit 8 ro 40 1.32790.7:0 bit rate bit 7 to bit 0 ro 72 bit(s) name description r/w 1 default value (dec) 1.32791.7:0 protocol supports 10gbe ro 1 bit(s) name description r/w 1 default value (dec) 1.32792.7:0 standards compliance code supports 10gbase-lr ro 2 1.32793.15:0 reserved n/a 0 bit(s) name description r/w 1 default value (dec) 1.32802.7:0 transmission range bit 15 (msb) to bit 8 ro 3 1.32803.7:0 transmission range bit 7 to bit 0 ro 232 bit(s) name description r/w 1 default value (dec) 1.32804.5 fiber type sm generic ro 32 1.32805.0 reserved n/a 0 bit(s) name description r/w 1 default value (dec) 1.32806.7:0 wavelength bits 23-16 ro 1 1.32807.7:0 wavelength bits 15-8 ro 255 1.32808.7:0 wavelength bits 7-0 ro 184 36 register 1.32818 to 1.32821 - package identifier (oui) = xenpak register 1.32822 to 1.32825 - vendor (oui) = agilent register 1.32826 to 1.32841 - vendor name (ascii) note: 1. rw = read/write, ro = read only. bit(s) name description r/w 1 default value (dec) 1.32818.7:0 package identifier package identifier ro 0 1.32819.7:0 package identifier package identifier ro 65 1.32820.7:2 package identifier package identifier ro 244 1.32820.1:0 nvr address nvr device address ro 1.32821.7:5 nvr address nvr device address ro 32 1.32821.4:1 revision number revision number ro 1.32821.0 reserved reserved bit(s) name description r/w 1 default value (dec) 1.32822.7:0 vendor oui vendor oui ro 0 1.32823.7:0 vendor oui vendor oui ro 51 1.32824.7:2 vendor oui vendor oui ro 44 1.32824.1:0 model no model number ro 1.32825.7:4 model no model number ro 0 1.32825.3:0 rev no revision number ro bit(s) name description r/w 1 default value 1.32826.7:0 vendor name vendor name byte 15 (msb:lsb) ro a (65) 1.32827.7:0 vendor name vendor name byte 14 (msb:lsb) ro g (71) 1.32828.7:0 vendor name vendor name byte 13 (msb:lsb) ro i (73) 1.32829.7:0 vendor name vendor name byte 12 (msb:lsb) ro l (76) 1.32830.7:0 vendor name vendor name byte 11 (msb:lsb) ro e (69) 1.32831.7:0 vendor name vendor name byte 10 (msb:lsb) ro n (78) 1.32832.7:0 vendor name vendor name byte 9 (msb:lsb) ro t (84) 1.32833.7:0 vendor name vendor name byte 8 (msb:lsb) ro space (32) 1.32834.7:0 vendor name vendor name byte 7 (msb:lsb) ro space (32) 1.32835.7:0 vendor name vendor name byte 6 (msb:lsb) ro space (32) 1.32836.7:0 vendor name vendor name byte 5 (msb:lsb) ro space (32) 1.32837.7:0 vendor name vendor name byte 4 (msb:lsb) ro space (32) 1.32838.7:0 vendor name vendor name byte 3 (msb:lsb) ro space (32) 1.32839.7:0 vendor name vendor name byte 2 (msb:lsb) ro space (32) 1.32840.7:0 vendor name vendor name byte 1 (msb:lsb) ro space (32) 1.32841.7:0 vendor name vendor name byte 0 (msb:lsb) ro space (32) 37 register 1.32842 to 1.32857 - vendor part number (ascii) register 1.32858 to 1.32859 - vendor revision (ascii) register 1.32860 to 1.32875 - vendor serial number (ascii) note: 1. rw = read/write, ro = read only. bit(s) name description r/w 1 default value (dec) 1.32842.7:0 vendor part no vendor part no. byte 15 (msb:lsb) ro h (72) 1.32843.7:0 vendor part no vendor part no. byte 14 (msb:lsb) ro f (70) 1.32844.7:0 vendor part no vendor part no. byte 13 (msb:lsb) ro c (67) 1.32845.7:0 vendor part no vendor part no. byte 12 (msb:lsb) ro t (84) 1.32846.7:0 vendor part no vendor part no. byte 11 (msb:lsb) ro - (45) 1.32847.7:0 vendor part no vendor part no. byte 10 (msb:lsb) ro 7 (55) 1.32848.7:0 vendor part no vendor part no. byte 9 (msb:lsb) ro 0 (48) 1.32849.7:0 vendor part no vendor part no. byte 8 (msb:lsb) ro 1 (49) 1.32850.7:0 vendor part no vendor part no. byte 7 (msb:lsb) ro x (88) 1.32851.7:0 vendor part no vendor part no. byte 6 (msb:lsb) ro b (66) 1.32852.7:0 vendor part no vendor part no. byte 5 (msb:lsb) ro space (32) 1.32853.7:0 vendor part no vendor part no. byte 4 (msb:lsb) ro space (32) 1.32854.7:0 vendor part no vendor part no. byte 3 (msb:lsb) ro space (32) 1.32855.7:0 vendor part no vendor part no. byte 2 (msb:lsb) ro space (32) 1.32856.7:0 vendor part no vendor part no. byte 1 (msb:lsb) ro space (32) 1.32857.7:0 vendor part no vendor part no. byte 0 (msb:lsb) ro space (32) bit(s) name description r/w 1 default value (dec) 1.32858.7:0 vendor rev revision upper byte (msb:lsb) ro 0 1.32859.7:0 vendor rev revision lower byte (msb:lsb) ro 0 bit(s) name description r/w 1 default value 1.32860.7:0 vendor serial no vendor serial no. byte 15 (msb:lsb) 1.32861.7:0 vendor serial no vendor serial no. byte 14 (msb:lsb) 1.32862.7:0 vendor serial no vendor serial no. byte 13 (msb:lsb) ro - 1.32863.7:0 vendor serial no vendor serial no. byte 12 (msb:lsb) ro - 1.32864.7:0 vendor serial no vendor serial no. byte 11 (msb:lsb) ro - 1.32865.7:0 vendor serial no vendor serial no. byte 10 (msb:lsb) ro - 1.32866.7:0 vendor serial no vendor serial no. byte 9 (msb:lsb) ro - 1.32867.7:0 vendor serial no vendor serial no. byte 8 (msb:lsb) ro - 1.32868.7:0 vendor serial no vendor serial no. byte 7 (msb:lsb) ro - 1.32869.7:0 vendor serial no vendor serial no. byte 6 (msb:lsb) ro - 1.32870.7:0 vendor serial no vendor serial no. byte 5 (msb:lsb) ro - 1.32871.7:0 vendor serial no vendor serial no. byte 4 (msb:lsb) ro - 1.32872.7:0 vendor serial no vendor serial no. byte 3 (msb:lsb) ro - 1.32873.7:0 vendor serial no vendor serial no. byte 2 (msb:lsb) ro - 1.32874.7:0 vendor serial no vendor serial no. byte 1 (msb:lsb) ro - 1.32875.7:0 vendor serial no vendor serial no. byte 0 (msb:lsb) ro - 38 register 1.32876 to 1.32885 - date code (ascii) register 1.32886 - 5 v stressed environment register 1.32887 - 3.3 v stressed environment register 1.32888 - aps stressed environment register 1.32889 - aps voltage register 1.32890 - dom capability register 1.32891 - reversed register 1.32894 - 1.32941 customer writeable area bit(s) name description r/w 1 default value 1.32876.7:0 year (1000's) year in 1000's (bit 7=msb, bit 0=lsb) 1.32877.7:0 year (100's) year in 100's (bit 7=msb, bit 0=lsb) 1.32878.7:0 year (10's) year in 10's (bit 7=msb, bit 0=lsb) ro - 1.32879.7:0 year (1's) year units (bit 7=msb, bit 0=lsb) ro - 1.32880.7:0 month (10's) month in 10's (bit 7=msb, bit 0=lsb) ro - 1.32881.7:0 month (1's) month in units (bit 7=msb, bit 0=lsb) ro - 1.32882.7:0 day (10's) day in 10's (bit 7=msb, bit 0=lsb) ro - 1.32883.7:0 day (1's) day in units (bit 7=msb, bit 0=lsb) ro - 1.32884.7:0 lot code (10's) lot code in 10's (bit 7=msb, bit 0=lsb) ro - 1.32885.7:0 lot code (1's) lot code in units (bit 7=msb, bit 0=lsb) ro - bit(s) name description r/w 1 default value 1.32886.7:0 5v supply 5 v stressed environment reference ro 0 bit(s) name description r/w 1 default value 1.32887.7:0 3.3v supply 3.3 v stressed environment reference ro 32 bit(s) name description r/w 1 default value 1.32888.7:0 aps supply aps stressed environment reference ro 1 bit(s) name description r/w 1 default value 1.32889.7:0 aps voltage nominal aps voltage (1.8v) ro 16 bit(s) name description r/w 1 default value 1.32890.7 status dom control/status register: 0 = not implemented 1 = implemented ro 0 1.32890.6 dom set set when dom implemented ro 0 1.32890.5 wdm capability wdm lane by lane dom capability: setting this bit indicates that registers a0co-a0ff are valid. setting this bit will not override indications placed in register a06f (dom capability) ro 0 1.32890.4 laser bias scale laser bias scale factor: 0 = 2 a 1 = 10 a ro 0 1.32890.3 reserved ro 0 1.32890.2:0 external dom address of external dom device ro 0 bit(s) name description r/w 1 default value 1.32891.7:0 dom control/status dom control/status ro bit(s) name description r/w 1 default value 1.32894.7:0 start of writeable area start of customer writeable area ro 1.32941.7:0 end of writeable area end of customer writeable area ro note: 1. rw = read/write, ro = read only. 39 register 1.32942 to 1.33030 - vendor specific register 1.33030 - extended vendor specific register 1.36864 rx_alarm control (see also table 1.36867 rx_alarm status) register 1.36865 tx_alarm control (see also table 1.36868 tx_alarm status) bit(s) name description r/w 1 default value 1.32942.7:0 to 1.33030.7:0 vendor specific ro bit(s) name description r/w 1 default value 1.33031.7:0 extended vendor specific ro bit(s) name description r/w 1 default value 1.36864. 15:11 reserved reserved ro 0 1.36864. 6 phy_xs receive buffer error enable 1 = phy_xs receive buffer over/underflow error enable 0 = disabled rw 0 1.36864. 5 receive optical power fault 1 = receive optical power fault enable 0 = receive optical power fault disable 1.36864. 4 pma/pmd local fault 1 = pma/pmd receiver local fault enable 0 = pma/pmd receiver local fault disable 1 1.36864. 3 pcs local fault 1 = pcs receiver local fault enable 0 = pcs receiver local fault disable rw 1 1.36864.2 pcs receive code 1 = violation enable 0 = violation disable 1.36864.1 rx flag 1 = enabled 0 = disabled rw 0 1.36864.0 phy xs receive local fault 1 = phy xs receive local fault enable 0 = phy xs receive local fault disable rw 1 bit(s) name description r/w 1 default value 1.36865. 15:11 reserved reserved ro 0 1.36865. 10 phy_xs code violation error 1 = phy_xs code violation error enabled 0 = phy_xs code violation error disabled rw note 3 1.36865. 9 laser bias current fault 1 = laser bias current fault enable 0 = laser bias current fault disable note 2 0 note 2 1.36865. 8 laser temp fault 1 = laser temperature fault enable 0 = laser temperature fault disable note 2 0 1.36865. 7 laser output fault 1 = laser output power fault enable 0 = laser output power fault disable note 2 0 1.36865. 6 transmitter fault 1 = transmitter fault enable 0 = transmitter fault disable rw 1 1.36865. 5 transmitter loss of lock 1 = transmitter loss of lock enabled 0 = transmitter loss of lock disabled rw note 3 1.36865. 4 pma/pmd transmit fault 1 = pma/pmd transmitter local fault enable 0 = pma/pmd transmitter local fault disable note 2 1 1.36865.3 pcs transmit fault 1 = pcs transmit local fault enable 0 = pcs transmit local fault disable rw 1 1.36865.2 pcs buffer over/underflow 1 = pcs buffer over/underflow enabled 0 = pcs buffer over/underflow disabled rw 0 1.36865.1 tx flag 1 = tx flag enabled 0 = tx flag disabled rw 0 1.36865.0 phy xs transmit fault 1 = phy xs transmit local fault enable 0 = phy xs transmit local fault disable rw 1 note: 1. rw = read/write, ro = read only. 2. optional features that are not implemented shall have their enable bit forced to zero. when implemented, the default value f or the control bit shall be 1. 3. the default value for a vendor specific bit shall be vendor specific. 40 register 1.36866 - lasi control (see also table 1.36869 lasi status) register 1.36867 - rx_alarm status (see also table 1.36864 - rx_alarm control) register 1.36868 - tx_alarm status (see also table 1.36865 tx_alarm control) bit(s) name description r/w 1 default value 1.36866.15:8 reserved reserved ro 0 1.36866. 6 mon3p3v_in supply too low 1 = enable detection of supply too low 0 = disable detection of supply too low rw 1.36866.5 3.3v supply too low 1 = enable detection of supply too low 0 = disable detection of supply too low rw 0 1.36866.4 1.8v supply too low 1 = enable detection of supply too low 0 = disable detection of supply too low rw 0 1.36866.3 lasi test data 1 = enable lasi test data 0 = disable lasi test data rw 0 1.36866. 2 rx alarm 1 = rx_alarm enable 0 = rx alarm disable rw 0 1.36866. 1 tx alarm 1 = tx_alarm enable 0 = tx alarm disable rw 0 1.36866. 0 ls alarm 1 = ls_alarm enable 0 = ls alarm disable rw 0 bit(s) name description r/w 1 default value 1.36867.15:11 reserved reserved ro/rw 1.36867.6 phy_xs receive buffer error enable 1 = phy xs receive buffer over/underflow enabled 0 = phy xs receive buffer over/underflow disabled ro/lh 1.36867.5 receive optical power fault local fault condition detected in optical power fault ro/lh 1.36867.4 pma/pmd receive local fault pma/pmd receive local fault ( a mirror of 1.8.10) ro/lh 1.36867.3 pcs receive local fault pcs receive local fault (a mirror of 3.8.10) ro/lh 1.36867.2 pcs receive code violation local fault condition detected in code violation ro/lh 1.36867.1 rx flag ro/lh 1.36867.0 phy-xs receive local fault phy_xs receive local fault. (a mirror of 4.8.10) ro/lh bit(s) name description r/w 1 default value 1.36868. 15:11 reserved reserved ro 1.36868. 10 phy_xs code violation enable phy_xs code violation error enable ro/lh 1.36868. 9 laser bias fault adc channel 2 laser bias current fault ro/lh 1.36868. 8 laser temp fault adc channel 1 laser temperature fault ro/lh 1.36868. 7 laser power fault adc channel 0 laser output power fault ro/lh 1.36868. 6 transmitter fault transmitter fault ro/lh 1.36868. 5 transmitter loss of lock ro/lh 1.36868. 4 pma/pmd transmit local fault pma/pmd transmitter local fault (linked to 1.8.11) ro/lh 1.36868.3 pcs transmit local fault pcs transmit local fault (linked to 3.8.11) ro/lh 1.36868.2 pcs buffer over/underflow error linked to 4.49154.8:9 ro/lh 1.36868.1 tx_flag ro/lh 1.36868.0 phy xs transmit local fault phy xs transmit local fault (linked to 4.8.11) ro/lh note: 1. rw = read/write, ro = read only, lh = latch high, clear on read (note that if the condition exists following register read, t he bit will not be cleared). 41 register 1.36869 - lasi status (see also table 1.36866 lasi control) register 1.49153 - extended pma features notes : 1. rw = read/write, ro = read only, lh = latch high, clear on read (note that if the condition exists following register read, t he bit will not be cleared. 2. the rx_alarm and tx_alarm indications are the logic or of the contents of registers 0x9003 and 0x9004 respectively. therefor e, these alarms will persist until the bit(s) reflecting the source of interrupt are cleared. bit(s) name description r/w 1 default value 1.36869.15:7 reserved reserved ro 1.36869.6 mon3p3v_in supply alarm 1 = 3.3v supply too low 0 = no alarm ro/lh 1.36869.5 3.3v supply alarm 1 = 3.3v supply too low 0 = no alarm ro/lh 1.36869.4 1.8v supply alarm 1 = 1.8v supply too low 0 = no alarm ro/lh 1.36869.3 lasi test data local fault condition detected in test data rw 1.36869.2 rx_alarm 1 = local fault condition detected in rx_alarm 0 = no alarm ro 2 1.36869.1 tx_alarm 1 = local fault condition detected in tx_alarm 0 = no alarm ro 2 1.36869.0 ls_alarm 1 = local fault condition detected in status change 0 = no status change lh bit(s) name description r/w 1 default value 1.49153.15:11 reserved n/a 1.49153.10 rxlosb_i override 1 = rxlosb_i override 0 = no override rw 0 1.49153.9 pma network loopback data out 1 = transmit all idles at rxxaui when in network loopback mode 0 = receive data at rxxaui when in network loopback mode rw 1.49153.8:5 reserved n/a 1.49153.4 pma network loopback mode 1 = enable network loopback 0 = disable network loopback rw 1.49153.3 reserved n/a 1.49153.2 refmon 0 = refclk present ro 1 1.49153.1 syn_err 1 = recovered clock rate error ro 1 1.49153.0 txlock 1 = fiber transmit pll in lock ro 1 42 register 1.49155 - pma/pmd vendor specific register 1.49156 - pma/pmd vendor specific checksum register 1.49188 - pma vendor specific bit(s) name description r/w 1 default value 1.49155.15:14 eeprom test mode 00 = 37khz 01 = high frequency test mode 10 = debug mode - do not use 11 = debug mode - do not use rw 1.49155.13 eeprom detect 1 = detected ro 1.49155.12 eeprom error 1 = eeprom error ro/lh 1.49155.11 eeprom active 1 = eeprom access in progress, mdio writes to eeprom registers ignored ro 1.49155.10:8 reserved ro 1.49155.7 eeprom checksum ok 1 = ok ro/lh 1.49155.6 reserved ro 1.49155.5:4 eeprom 256 byte read cycle burst size size bit1 bit0 1 0 0 8 0 1 16 1 0 256 1 1 rw 11 1.49155.3:2 reserved ro 1.49155.1:0 eeprom 256 byte write cycle burst size size bit1 bit0 1 0 0 8 0 1 16 1 0 1 1 1 rw 01 bit(s) name description r/w 1 default value 1.49156.15:8 eeprom calculated checksum ro 1.49156.7:4 reserved ro 1.49156.3:2 eeprom 256 byte write cycle burst size size bit1 bit0 1 0 0 8 0 1 16 1 0 1 1 1 rw 01 1.49156.1:0 dom write command bit1 bit0 command 0 0 reserved 0 1 reserved 1 0 reserved 1 1 write 256 bytes rw bit(s) name description r/w 1 default value 1.49188.15:4 reserved ro 1.49188.3 txpllout frequency selection 1 = 10 ghz 0 = 156 mhz rw 0 1.49188.2 reserved ro 1.49188.1 txpllout enable 1 = enabled 0 = disabled rw 0 1.49188.0 eeprom_scl tristate 1 = tristate 0 = not tristate rw 0 notes : 1. rw = read/write, ro = read only, lh = latch high, clear on read (note that if the condition exists following register read, t he bit will not be cleared. 43 HFCT-701XB device 3 pcs registers device from decimal hex to decimal hex register name 3 0 0 pcs control 1 31 1 pcs status 1 32233pcs device identifier 3 4 4 pcs speed ability 35566pcs devices in package 3 7 7 10g pcs control 2 3 8 8 10g pcs status 2 3 32 20 10gbase-r pcs status 1 3 33 21 10gbase-r pcs status 2 33422372510gbase-r pcs test pattern seed a 33826412910gbase-r pcs test pattern seed b 3 42 2a 10gbase-r pcs test pattern control 3 43 2b 10gbase-r pcs test pattern error counter 3 3 3 49152 c000 pcs extended features 3 49153 c0001 49157 c005 3 49158 c006 49169 c011 pcs vendor specific 44 register 3.0 - pcs control 1 register 3.1 - pcs status 1 register 3.2 to 3.3 - pcs device identifier a mirror of registers 1.2 to 1.3. register 3.4 - pcs speed ability register 3.5 to 3.6 - pcs devices in package a mirror of registers 1.5 to 1.6. note: 1. rw = read/write, sc = self clearing, ro = read only, ll = latching low. bit(s) name description r/w 1 default value 3.0.15 pcs 64/66 reset 1 = pcs reset 0 = normal operation rw/sc 3.0.14 pcsloopback 1 = enable loopback mode 0 = disable loopback mode rw 0 3.0.13 speed selection 1 = operation at 10 gb/s and above 0 = unspecified rw 3.0.12 reserved rw 3.0.11 low power 1 = low power mode 0 = normal operation rw 3.0.10:7 reserved rw 3.0.6 speed selection 1 = operation at 10 gb/s and above 0 = unspecified rw 3.0.5:2 speed selection 5 4 3 2 0 0 0 0 = 10 gb/s rw 0000 3.0.1:0 reserved rw bit(s) name description r/w 1 default value 3.1.15:8 reserved ro 3.1.7 local fault 1 = local fault condition detected 0 = local fault condition not detected (set to 1 when either 3.8.11 or 3.8.10 set to 1) ro 3.1.6:3 reserved n/a 3.1.2 pcs receive link status 1 = pcs receive link up 0 = pcs receive link down ro/ll 3.1.1 low power ability 1 = pcs supports low power mode 0 = pcs does not support low power mode ro 3.1.0 reserved n/a ro bit(s) name description r/w 1 default value 3.4.15:1 reserved ro n/a 3.4.0 10 g capable 1 = pcs capable of operating at 10 gb/s 0 = pcs is not capable of operating at 10 gb/s ro 1 45 register 3.7 - 10 g pcs control 2 register 3.8 - 10 g pcs status 2 register 3.32 - 10gbase-r pcs status 1 notes : 1. rw = read/write, ro = read only, lh = latch high, clear on read (note that if the condition exists following register read, t he bit will not be cleared. bit(s) name description r/w 1 default value 3.7.15:2 reserved n/a 3.7.1:0 pcs type selection 1 0 0 0 = select 10gbase-r pcs type rw 00 bit(s) name description r/w 1 default value 3.8.15:14 device present 15 14 1 0 = device responding at this address 1 1 = no device responding at this address 0 1 = no device responding at this address 0 0 = no device responding at this address ro 3.8.13:12 reserved n/a ro 3.8.11 transmit local fault 1 = local fault condition on transmit path 0 = no local fault condition on transmit path ro/lh 3.8.10 receive local fault 1 = local fault condition on receive path 0 = no local fault condition on receive path ro/lh 3.8.9:3 reserved n/a ro 3.8.2 10gbase-w capable 1 = pcs is able to support 10gbase-w pcs type 0 = pcs is not able to support 10gbase-w pcs type ro 3.8.1 10gbase-x capable 1 = pcs is able to support 10gbase-x pcs type 0 = pcs is not able to support 10gbase-x pcs type ro 3.8.0 10gbase-r capable 1 = pcs is able to support 10gbase-r pcs type 0 = pcs is not able to support 10gbase-r pcs type ro bit(s) name description r/w 1 default value 3.32.15:13 reserved ro 3.32.12 10gbase-r receive link status 1 = 10gbase-r pcs receive link up 0 = 10gbase-r pcs receive link down ro 3.32.11:3 reserved ro 3.32.2 prbs31 pattern testing ability 1 = pcs is able to support prbs31 pattern testing 0 = pcs is not able to support prbs31 pattern testing ro 3.32.1 10gbase-r pcs high ber 1 = 10gbase-r pcs reporting a high ber 0 = 10gbase-r pcs not reporting a high ber ro 3.32.0 10gbase-r pcs block lock 1 = 10gbase-r pcs locked to received blocks 0 = 10gbase-r pcs not locked to received blocks ro 46 register 3.33 - 10gbase-r pcs status 2 register 3.34 to 3.37 - 10gbase-r pcs test pattern seed a register 3.38 to 3.41 - 10gbase-r pcs test pattern seed b register 3.42 - 10gbase-r pcs test pattern control notes : 1. rw = read/write, ro = read only, ll = latching low, lh = latch high, clear on read (note that if the condition exists followi ng register read, the bit will not be cleared, nr = non roll-over. bit(s) name description r/w 1 default value 3.33.15 latched block lock 1 = pcs has reported block lock since last read 0 = pcs has not reported block lock since last read ro/ll 3.33.14 latched high ber 1 = pcs has reported high ber since last read 0 = pcs has not reported high ber since last read ro/lh 3.33.13:8 ber ber counter ro/nr 3.33.7:0 errored blocks jitter pattern checker ro/nr bit(s) name description r/w 1 default value 3.37.15:10 reserved value always 0, writes ignored rw 3.37.9:0 test pattern seed a 3 test pattern seed a bits 48-57 rw 3.36.15:0 test pattern seed a 2 test pattern seed a bits 32-47 rw 3.35.15:0 test pattern seed a 1 test pattern seed a bits 16-31 rw 3.34.15:0 test pattern seed a 0 test pattern seed a bits 0-15 rw bit(s) name description r/w 1 default value 3.41.15:10 reserved value always 0, writes ignored rw 3.41.9:0 test pattern seed b 3 test pattern seed b bits 48-57 rw 3.40.15:0 test pattern seed b 2 test pattern seed b bits 32-47 rw 3.39.15:0 test pattern seed b 1 test pattern seed b bits 16-31 rw 3.38.15:0 test pattern seed b 0 test pattern seed b bits 0-15 rw bit(s) name description r/w 1 default value 3.42.15:6 reserved value always 0, writes ignored rw 3.42.5 prbs31 receive test pattern 1 = enable prbs31 test pattern mode on the receive path 0 = disable prbs31 test pattern mode on the receive path rw 0 3.42.4 prbs31 transmit test pattern 1 = enable prbs31 test pattern mode on the transmit path 0 = disable prbs31 test pattern mode on the transmit path rw 0 3.42.3 transmit test pattern 1 = enable transmit test pattern testing 0 = disable transmit test pattern testing rw 3.42.2 receive test pattern 1 = enable receive test pattern testing 0 = disable receive test pattern testing rw 3.42.1 test pattern select 1 = square wave test pattern 0 = pseudo random test pattern rw 3.42.0 data pattern select 1 = zeros data pattern 0 = lf data pattern rw 47 register 3.43 - 10gbase-r pcs test pattern error counter register 3.49152 - pcs extended features notes : 1. rw = read/write, ro = read only, lh = latch high, clear on read (note that if the condition exists following register read, t he bit will not be cleared, nr = non roll-over. bit(s) name description r/w 1 default value 3.43.15:0 test pattern error counter error counter lsb = bit 0 msb = bit 15 ro/nr bit(s) name description r/w 1 default value 3.49152.15:8 diagnostic register diagnostic register ro 3.49152.7:6 reserved n/a 3.49152.5 pcs loopback data out 1 = transmit data at txout when in pcs loopback mode 0 = transmit a square wave when in pcs loopback mode rw 0 3.49152.4 reset transmit pcs 1 = not reset 0 = resetnote: not self clearing rw 1 3.49152.3 reset receive pcs 1 = not reset 0 = resetnote: not self clearing rw 1 3.49152.2 tx scrambler bypass 1 = bypass rw 0 3.49152.1 rx scrambler bypass 1 = bypass rw 0 3.49152.0 64/66 encoder error 1 = error ro/lh 0 bit(s) name description r/w 1 default value 3.49158.15:7 vendor specific reserved ro 3.49158.6:0 receive frame offset ro bit(s) name description r/w 1 default value 3.49159.15:0 first 16 bits of xgmii bus error flag 1 = error at this bit location ro/lh bit(s) name description r/w 1 default value 3.49160.15:0 second 16 bits of xgmii bus error flag 1 = error at this bit location ro/lh bit(s) name description r/w 1 default value 3.49161.15:6 vendor specific reserved ro 3.49161.5 rx_idle_err_flag received a full packet but with start or idle errors ro/lh 3.49161.4 rx_start_err_flag received a full packer but with preamble errors ro/lh 3.49161.3 rx_data_err_flag received a full packet but long packet ro/lh 3.49161.2 rx_long_pkt_flag received a full packet but long packet ro/lh 3.49161.1 rx_short_pkt_flag received a full packet but short packet ro/lh 3.49161.0 rx_term_err_flag set if terminate received but the next byte is not an idle ro/lh bit(s) name description r/w 1 default value 3.49152.15:0 3.49153.15:0 3.49154.15:0 3.49155.15:0 3.49156.15:0 3.49157.15:0 diagnostic registers register 3.49152 - 3.49157 - pcs vendor specific register 3.49158 - pcs vendor specific register 3.49159 - pcs vendor specific receive path packet checker register 3.49160 - pcs vendor specific receive path packet checker register 3.49161 - pcs vendor specific receive path packet checker 48 register 3.49162 - pcs vendor specific transmit path packet checker register 3.49163 - pcs vendor specific transmit path packet checker register 3.49164 - pcs vendor specific packet generator/checker register 3.49165 - pcs vendor specific packet generator register 3.49166 - pcs vendor specific packet generator register 3.49167 - pcs vendor specific packet generator notes : 1. rw = read/write, ro = read only, lh = latch high, clear on read (note that if the condition exists following register read, t he bit will not be cleared. bit(s) name description r/w 1 default value 3.49162.15:0 first 16 bits of xgmii bus error flag 1 = error at this bit location ro/lh bit(s) name description r/w 1 default value 3.49163.15:0 second 16 bits of xgmii bus error flag 1 = error at this bit location ro/lh bit(s) name description r/w 1 default value 3.49164.15:6 packet generator idle size rw 3.49164.5 tx_idle_err_flag received a full packet but with start or idle errors ro/lh 3.49164.4 tx_start_err_flag received a full packet but with preamble errors ro/lh 3.49164.3 tx_data_err_flag received a full packet but with long packet ro/lh 3.49164.2 tx_long_pkt_flag received a full packet but with long packet ro/lh 3.49164.1 tx_short_pkt_flag received a full packet but with short packet ro/lh 3.49164.0 tx_term_err_flag set if terminate received but the next byte is not an idle ro/lh bit(s) name description r/w 1 default value 3.49165.15:0 fixed pattern first 16 bits of xgmii rw bit(s) name description r/w 1 default value 3.49166.15:0 fixed pattern second 16 bits of xgmii rw bit(s) name description r/w 1 default value 3.49167.15:14 vendor specific reserved ro 3.49167.13 tx path pattern checker 1 = enabled 0 = disabled rw 0 3.49167.12 tx path pattern generator 1 = enabled 0 = disabled rw 0 3.49167.11 rx path pattern checker 1 = enabled 0 = disabled rw 0 3.49167.10 rx path pattern generator 1 = enabled 0 = disabled rw 0 3.49167.9 packet type 1 = increment pattern 0 = fixed pattern rw 3.49167.8:0 data packet size divided by 4 rw 49 register 3.49169 - pcs vendor specific note: 1. rw = read/write, ro = read only. HFCT-701XB device 4 phyxs registers bit(s) name description r/w 1 default value 3.49169.15:2 reserved ro 3.49169.1 gearbox fifo error diagnostic register ro 3.49169.0 frame sync fifo error diagnostic register ro e c i v e dm o r f l a m i c e dx e h o t l a m i c e dx e h e m a n r e t s i g e r 40 0 1 l o r t n o c s x y h p 41 1 1 s u t a t s s x y h p 42 2 3 3 r e i f i t n e d i e c i v e d s x y h p 44 4 y t i l i b a d e e p s s x y h p 45 5 6 6 e g a k c a p n i s e c i v e d s x y h p 48 8 2 s u t a t s s x y h p 44 1e 5 1f r e i f i t n e d i e g a k c a p s x y h p 44 28 1s u t a t s e n a l s x g x y h p g 0 1 50 register 4.0 - phy_xs control 1 register 4.1 - phy_xs status 1 register 4.2 to 4.3 - device identifier a mirror of registers 1.2 to 1.3. register 4.4 - phy_xs speed ability register 4.5 to 4.6 - device in package a mirror of registers 1.5 to 1.6. notes : 1. rw = read/write, sc = self clearing, ro = read only, ll = latching low. bit(s) name description r/w 1 default value 4.0.15 global reset 1 = reset 0 = normal operation rw/sc 4.0.14 loopback 1 = enable phy xs loopback mode 0 = disable phy xs loopback mode rw 0 4.0.13 speed selection 1 = operation at 10 gb/s and above 0 = unspecified rw 4.0.12 reserved rw 4.0.11 low power 1 = low power mode 0 = normal operation rw 4.0.10:7 reserved rw 4.0.6 speed selection 1 = operation at 10 gb/s and above 0 = unspecified rw 1 4.0.5:2 speed selection 5 4 3 2 0 0 0 0 = 10 gb/s rw 0000 4.0.1:0 reserved value always 0, writes ignored rw bit(s) name description r/w 1 default value 4.1.15:8 reserved n/a ro 4.1.7 local fault 1 = local fault condition detected on phy xs 0 = local fault condition not detected on phy xs ro 4.1.6:3 reserved n/a ro 4.1.2 phy xs transmit link status 1 = the phy xs transmit link is up 0 = the phy xs transmit link is down ro/ll 4.1.1 low power ability 1 = phyxs supports low power mode 0 = phyxs does not support low power mode ro 1 4.1.0 reserved n/a ro bit(s) name description r/w 1 default value 4.4.15:1 reserved for future speeds ro 4.4.0 10 g capable 1 = phyxs is capable of operating at 10 gb/s 0 = phyxs is not capable of operating at 10 gb/s ro 1 51 register 4.8 - phy_xs status 2 register 4.14 to 4.15 - package identifier (oui) a mirror of registers 1.32818 to 1.32821. register 4.24 - 10g phy_xgxs lane status register 4.25 - 10 g phy_xgxs test control notes : 1. rw = read/write, ro = read only, lh = latch high, clear on read (note that if the condition exists following register read, t he bit will not be cleared. bit(s) name description r/w 1 default value 4.8.15:14 device present 15 14 1 0 = device responding at this address 1 1 = no device responding at this address 0 1 = no device responding at this address 0 0 = no device responding at this address ro 10 4.8.13:12 reserved n/a 4.8.11 transmit local fault 1 = local fault condition on transmit path of phy xs 0 = no local fault condition on transmit path of phy xs ro/lh 4.8.10 receive local fault 1 = fault condition on receive path of phy xs 0 = no fault condition on receive path of phy xs ro/lh 4.8.9:0 reserved n/a ro bit(s) name description r/w 1 default value 4.24.15:13 reserved n/a ro 4.24.12 phy xgxs lane alignment status 1 = phy xgxs transmit lanes aligned 0 = phy xgxs transmit lanes not aligned ro 4.24.11 pattern testing ability 1 = phy xgxs is able to generate test patterns 0 = phy xgxs is not able to generate test patterns ro 1 4.24.10 phy xgxs loopback ability 1 = phy xgxs has the ability to perform a loopback function 0 = phy xgxs does not have the ability to perform a loopback function ro 1 4.24.9:4 reserved n/a ro 4.24.3 lane 3 sync 1 = lane 3 is synchronized 0 = lane 3 is not synchronized ro n/a 4.24.2 lane 2 sync 1 = lane 2 is synchronized 0 = lane 2 is not synchronized ro n/a 4.24.1 lane 1 sync 1 = lane 1 is synchronized 0 = lane 1 is not synchronized ro n/a 4.24.0 lane 0 sync 1 = lane 0 is synchronized 0 = lane 0 is not synchronized ro n/a bit(s) name description r/w 1 default value 4.25.15:3 reserved n/a rw 4.25.2 receive test pattern enable 1 = receive test pattern enabled 0 = receive test pattern not enabled rw 0 4.25.1:0 test pattern select 1 0 1 1 = reserved 1 0 = mixed frequency test pattern 0 1 = low frequency test pattern 0 0 = high frequency test pattern rw 52 register 4.49152 - phy_xs extended features register 4.49153 - phy_xs extended features notes : 1. rw = read/write, ro = read only. bit(s) name description r/w 1 default value 4.49152.15 xaui system loopback data out enable 1 = transmit data at txout when in phy_xs loopback mode 0 = transmit all 1's when in phy_xs loopback mode rw 0 4.49152.14 xaui system loopback (tx - >rx path) enable 1 = enable xaui loopback rw 0 4.49152.13 xaui prbs enable 1 = enable prbs rw 0 4.49152.12 xaui analog monitor point control 1 = xaui lane 3 recovered data 0 = xaui lane 3 recovered clock 4.49152.11:8 reserved n/a 4.49152.7 lane 3 locked 1 = lane 3 in lock ro n/a 4.49152.6 lane 2 locked 1 = lane 2 in lock ro n/a 4.49152.5 lane 1 locked 1 = lane 1 in lock ro n/a 4.49152.4 lane 0 locked 1 = lane 0 in lock ro n/a 4.49152.3 xaui pll locked 1 = xaui pll locked ro n/a 4.49152.2 xaui external reference clock mode 1 = external clock 0 = internal reference clock rw 0 4.49152.1 receive xgxs reset 1 = not reset 0 = reset note: not self clearing rw 1 4.49152.0 transmit xgxs reset 1 = not reset 0 = reset note: not self clearing rw 1 bit(s) name description r/w 1 default value 4.49153.15:8 reserved n/a ro 4.49153.7 xaui lane 7 prbs error 1 = error ro/lh 4.49153.6 xaui lane 6 prbs error 1 = error ro/lh 4.49153.5 xaui lane 5 prbs error 1 = error ro/lh 4.49153.4 xaui lane 4 prbs error 1 = error ro/lh 4.49153.3 xaui lane 3 prbs error 1 = error ro/lh - 4.49153.2 xaui lane 2 prbs error 1 = error ro/lh - 4.49153.1 xaui lane 1 prbs error 1 = error ro/lh - 4.49153.0 xaui lane 0 prbs error 1 = error ro/lh - 53 register 4.49154 - phy_xs vendor specific register 4.49155 - phy_xs vendor specific register 4.49156 - phy_xs vendor specific register 4.49157 - phy_xs vendor specific notes : 1. rw = read/write, ro = read only, lh = latch high, clear on read (note that if the condition exists following register read, t he bit will not be cleared. 2. this bit is linked to an mdio latched high diagnostic alarm register bit. when either register is read, both bits will be cl eared. bit(s) name description r/w 1 default value 4.49154.15:10 vendor specific reserved ro 4.49154.9 xgxs tx rate adjust overflow 1 = overflow(linked to 1.36868.2) ro/lh note 2 4.49154.8 xgxs tx rate adjust underflow 1 = underflow(linked to 1.36868.2) ro/lh note 2 4.49154.7 xgxs rx rate overflow 1 = overflow(linked to 1.36867.6) ro/lh note 2 4.49154.6 xgxs rx rate adjust underflow 1 = underflow(linked to 1.36867.6) ro/lh note 2 4.49154.5:0 vendor specific reserved ro - bit(s) name description r/w 1 default value 4.49155.15:12 sync offset xaui channel 3 ro 4.49155.11:8 sync offset xaui channel 2 ro 4.49155.7:4 sync offset xaui channel 1 ro 4.49155.3:0 sync offset xaui channel 0 ro bit(s) name description r/w 1 default value 4.49156.15:12 align offset xaui channel 3 ro 4.49156.11:8 align offset xaui channel 2 ro 4.49156.7:4 align offset xaui channel 1 ro 4.49156.3:0 align offset xaui channel 0 ro bit(s) name description r/w 1 default value 4.49157.15 phy_xs phase_err3 xaui lane 3 clock phase error, clear on read ro 4.49157.14 phy_xs phase_err2 xaui lane 2 clock phase error, clear on read ro 4.49157.13 phy_xs phase_err1 xaui lane 1 clock phase error, clear on read ro 4.49157.12 phy_xs phase_err0 xaui lane 0 clock phase error, clear on read ro 4.49157.11:0 vendor specific reserved ro 54 register 4.49158 - phy_xs vendor specific register 4.49160 - phy_xs vendor specific bit(s) name description r/w 1 default value 4.49158.15:8 vendor specific reserved ro 4.49158.7 lane 3 upper byte 10b/8b decode error ro/lh 4.49158.6 lane 2 upper byte 10b/8b decode error ro/lh 4.49158.5 lane 1 upper byte 10b/8b decode error ro/lh 4.49158.4 lane 0 upper byte 10b/8b decode error ro/lh 4.49158.3 lane 3 lower byte 10b/8b decode error ro/lh 4.49158.2 lane 2 lower byte 10b/8b decode error ro/lh 4.49158.1 lane 1 lower byte 10b/8b decode error ro/lh 4.49158.0 lane 0 lower byte 10b/8b decode error ro/lh bit(s) name description r/w 1 default value 4.49160.15:0 phy_xs receive code violation counter clear on read bit0 = lsb bit15 = msb note: in tx path ro/nr notes : 1. rw = read/write, ro = read only, lh = latch high, clear on read (note that if the condition exists following register read, t he bit will not be cleared, nr = non roll-over. 55 table 15. regulatory compliance - typical performance feature test method performance general telcordia gr-468-core qualified in accordance with remote terminal requirements electrostatic discharge - human body model mil std 883 method 3015 500 v electrostatic discharge - charged device model jedec jes d22-c101 500 v electrostatic discharge - contact discharge iec 61000-4-2 8000 v electromagnetic interference fcc class bcenelec en55022 class b (cispr 22b) vcci class 2 margins are dependant on customer board and chassis design immunity variation of iec 61000-4-3 a ber of better than 1e-12 was observed from a 10 v/m field swept from 80 mhz to 1 ghz, 80% am 1 khz. eye safety n/a for copper module. regulatory compliance the HFCT-701XB is intended to enable commercial system designers to develop equipment that complies with the various regulations governing certification of in formation technology equipment (see table 15). electrostatic discharge (esd) there are two design cases in which immunity to esd damage is important. the first case is during handling of the transceiver prior to pl ugging into the circuit board. it is important to use normal esd handling precautions for esd sensitive devices. these precautions include using grounded wrist straps, work benches and floor mats in esd controlled areas. the second case to consider is static charges to the exterior of the equipment chassis containing the transceiver parts. to the extent that the sc duplex connector is exposed to the outside of the equipment chassis it may be subject to whatever esd system level criteria that the equipment is intended to meet. electromagnetic interference (emi) most equipment design utilizing these high speed transceivers from agilent will be required to meet the requirements of fcc in the united states, cenelec en55022 (cispr 22) in europe and vcci in japan. performance of the HFCT-701XB transceiver is dependent upon customer board and chassis design. immunity equipment utilizing these transceivers will be subject to radio frequency electromagnetic fields in some environments. these transceivers have been characterized without the benefit of the normal equipment chassis enclosure and results are reported below. performance of a system containing these transceivers within a well- designed chassis enclosure is expected to be better than the results of these tests without a chassis enclosure. glossary phy = module = used interchangeably with hfct- 701xb in this document. network = used to indicate elements that are on the optical side of the module. network loopback = a signal path within the module from the optical input of the module to the optical output of the module. system = used to indicate elements that are on the electrical side of the module. system loopback = a signal path within the module from the electrical input of the module to the electrical output of the module. www.agilent.com/ semiconductors for product information and a complete list of distributors, please go to our web site. for technical assistance call: americas/canada: +1 (800) 235-0312 or (916) 788-6763 europe: +49 (0) 6441 92460 china: 10800 650 0017 hong kong: (+65) 6756 2394 india, australia, new zealand: (+65) 6755 1939 japan: (+81 3) 3335-8152(domestic/international), or 0120-61-1280(domestic only) korea: (+65) 6755 1989 singapore, malaysia, vietnam, thailand, philippines, indonesia: (+65) 6755 2044 taiwan: (+65) 6755 1843 data subject to change. copyright ? 2003 agilent technologies, inc. obsoletes: 5988-9263en february 20, 2004 5989-0376en |
Price & Availability of HFCT-701XB
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |